Strained-channel transistor structure with lattice-mismatched zone

ABSTRACT

A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device with lattice-mismatched zone and fabrication method thereof, and more specifically to a strained-channel transistor structure and fabrication method thereof.

[0003] 2. Description of the Related Art

[0004] Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of gate length and gate oxide thickness, has enabled a continuous improvement in speed performance, density, and cost per unit function of integrated circuits during the past few decades.

[0005] In order to further enhance performance of the transistor, strain may be introduced in the transistor channel to improve carrier mobility to enhance performance of the transistor in addition to device scaling. There are several existing approaches to introducing strain in a channel region of the transistor.

[0006] In one conventional approach, as described in a paper titled “NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures”, disclosed by J. Welser et al., published at the December 1992 International Electron Devices Meeting held in San Francisco, Calif., pp. 1000-1002, a relaxed silicon germanium (SiGe) buffer layer 110 is provided beneath channel region 126, as shown in FIG. 1A. In FIG. 1B and FIG. 1C, a simple model of different lattice constants is used to show the intersection between relaxed SiGe layer 114 of buffer layer 110 and strained-Si layer 130. In FIG. 1B, model 135 shows the natural lattice constant of Si, smaller than that of SiGe shown by model 115. In FIG. 1C, when a thin layer of epitaxial Si (model 135) is grown on relaxed SiGe layer 114 (model 115), unit cell 136 of Si shown in model 135 is stretched laterally so as to be under a biaxial tensile strain. The thin layer of epitaxial Si becomes strain-Si layer 130 shown in FIG. 1A. In FIG. 1A, a transistor formed on the epitaxial strained-Si layer 130 is therefore with a channel region 126 under the biaxial tensile strain. In this approach, relaxed SiGe layer 114 is a stressor that introduces strain in channel region 126. The stressor, in this case, is placed below channel region 126. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the aforementioned approach, the epitaxial silicon layer 130 is strained before forming the transistor. Therefore, there are some concerns about possible strain relaxation in the subsequent high temperature CMOS processes. Further, the approach is very expensive since SiGe buffer layer 110 with thickness in the order of micrometers has to be grown. Numerous dislocations exist in relaxed SiGe layer 114, some of which propagate to strained-Si layer 130, resulting in high defect density, thereby negatively affecting transistor performance.

[0007] In another approach, strain in a channel region is introduced after a transistor is formed. In this approach, a high stress film 220 is formed over a completed transistor structure 250, as shown in FIG. 2. High stress film 220, being a stressor, exerts significant influence on channel region 206, modifying silicon lattice spacing in channel region 206, and thus introducing strain in channel region 206. In this case, the stressor is placed above completed transistor structure 250, described in detail in a paper disclosed by A. Shimizu et al., entitled “Local mechanical stress control (LMC): a new technique for CMOS performance enhancement”, published in pp. 433-436 of the Digest of Technical Papers of the 2001 International Electron Device Meeting. The strain contributed by high stress film 220 is believed to be uniaxial in nature with a direction parallel to a source-to-drain direction. However, uniaxial tensile strain in the source-to-drain degrades hole mobility while uniaxial compressive strain degrades electron mobility. Ion implantation of germanium can be used to selectively relax the strain so that the hole or electron mobility is not degraded, but can be difficult to implement due to the close proximity of the N and P-channel transistors.

SUMMARY OF THE INVENTION

[0008] Thus, the main object of the present invention is to provide a transistor structure with a strained channel region.

[0009] Another object of the present invention is to provide a strained-channel transistor structure where portions of one or both of a source region and drain region adjacent to a strained channel region are lattice mismatched with respect to the channel region.

[0010] Another object of the present invention is to provide a fabrication method of a strained-channel transistor structure.

[0011] In order to achieve the above objects, the present invention provides a strained-channel transistor structure comprising a strained channel region, a gate dielectric layer, a gate electrode, and a source region and drain region. The substrate comprises a first semiconductor material with a first natural lattice constant. The gate dielectric layer is on the strained channel region. The gate electrode is on the gate dielectric layer. The source region and drain region are oppositely adjacent to the strained channel region. One or both of the source region and drain region comprise a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

[0012] The present invention further provides a fabrication method of a strained-channel transistor structure. First, a substrate having a channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric on the channel region, and a gate electrode on the gate dielectric layer is provided. Then, a first source region and drain region are formed oppositely adjacent to the channel region. Next, a spacer is formed on a sidewall of the gate electrode, covering a part of the surface of the substrate. Next, the surface of the substrate not covered by the spacer and gate electrode is recessed. Further, the recess is filled with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone straining the channel region. Finally, a second source region is formed adjacent to the first source region and a second drain region is formed adjacent to the first drain region, one or both of the second source region and second drain region comprising the lattice-mismatched zone.

[0013] The present invention further provides a fabrication method of a strained-channel transistor structure. First, a substrate having a channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric on the channel region, a gate electrode on the gate dielectric layer, a source region and drain region oppositely adjacent to the channel region, and a spacer on a sidewall of the gate electrode, covering a part of the surface of the substrate, is provided. Then, one or both of the source region and drain region is recessed. Finally, the recess is filled with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone straining the channel region.

[0014] The present invention further provides a fabrication method of a strained-channel transistor structure. First, a substrate having a channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric on the channel region, a gate electrode on the gate dielectric layer, and a spacer on a sidewall of the gate electrode, covering a part of the surface of the substrate, is provided. Then, the surface of the substrate not covered by the spacer and gate dielectric layer is recessed to form a recess. Finally, a source region and drain region are formed oppositely adjacent to the channel region, one or both of the source region and drain region comprising the lattice-mismatched zone.

[0015] The present invention further provides a fabrication method of a strained-channel transistor structure. First, a substrate having a channel region, comprising a semiconductor material, in a surface, a gate dielectric on the channel region, a gate electrode on the gate dielectric layer, a source region and drain region oppositely adjacent to the channel region, and a spacer on a sidewall of the gate electrode, covering a part of the surface of the substrate, is provided. Finally, an element with an atomic size different from that of the semiconductor material is implanted to form a lattice-mismatched zone in one or both of the source region and drain region straining the channel region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples with references made to the accompanying drawings, wherein:

[0017]FIGS. 1A through 1C are cross sections illustrating a conventional strained silicon transistor with a relaxed SiGe layer as a stressor to induce strain in the top epitaxial strained silicon layer.

[0018]FIG. 2 is a cross section illustrating another conventional strained silicon transistor introducing strain in the channel using a high stress film as a stressor.

[0019]FIG. 3A and FIG. 3B are cross sections illustrating strained-channel transistor structures in accordance with the first embodiment of the present invention.

[0020]FIGS. 4A through 4B are cross sections illustrating strained-channel transistor structures in accordance with the second embodiment of the present invention.

[0021]FIG. 5 is a flowchart illustrating, in detail, the fabrication method of a strained-channel transistor structure in accordance with the third embodiment of the present invention.

[0022]FIGS. 6A through 6F are cross sections illustrating steps of the fabrication method of a strained-channel transistor structure in accordance with the third embodiment of the present invention.

[0023]FIG. 7 is a flowchart illustrating, in detail, the fabrication method of a strained-channel transistor structure in accordance with the fourth embodiment of the present invention.

[0024]FIGS. 8A through 8D are cross sections illustrating steps of the fabrication method of a strained-channel transistor structure in accordance with the fourth embodiment of the present invention.

[0025]FIG. 9 is a flowchart illustrating, in detail, the fabrication method of a strained-channel transistor structure in accordance with the fifth embodiment of the present invention.

[0026]FIGS. 10A through 10G are cross sections illustrating steps of the fabrication method of a strained-channel transistor structure in accordance with the fifth embodiment of the present invention.

[0027]FIGS. 11A through 11D are cross sections illustrating steps of the fabrication method of a strained-channel transistor structure in accordance with the sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] The following embodiments are intended to illustrate the invention more fully without limiting their scope, since numerous modifications and variations will be apparent to those skilled in this art.

FIRST EMBODIMENT

[0029] In the first embodiment of the present invention, two kinds of stress modes exerted on the strained-channel region according to the present invention are discussed.

[0030] In FIG. 3A, a cross section of a strained-channel transistor structure 3 a in accordance with the first embodiment of the present invention is shown. Substrate 300 a, having a strained channel region 306 a in a surface, comprises a semiconductor material. Gate dielectric layer 312 a, preferably with a thickness between about 3 and 100 Å, is on the strained channel region 306 a. Gate electrode 314 a is on the gate dielectric layer 312 a. Spacer 316 a is on a sidewall of gate electrode 314 a and covers a part of the surface of substrate 300 a. Drain region 307 a, comprising drain extension region 301 a and deeper drain region 302 a, and source region 308 a, comprising source extension region 303 a and deeper source region 304 a, are oppositely adjacent to strained channel region 306 a. Lattice-mismatched zone 305 a, comprising another semiconductor material with a natural lattice constant different from that of substrate 300 a, may be in one or both of the deeper drain region 302 a and deeper source region 304 a. Strained channel region 306 a is therefore strained by the different lattice constants of strained channel region 306 a and lattice-mismatched zone 305 a.

[0031] In strained-channel transistor structure 3 a in accordance with the first embodiment of the present invention, substrate 300 a preferably comprises silicon, with a natural lattice constant of approximately 5.431 Å, and lattice-mismatched zone 305 a preferably comprises an alloy semiconductor material such as a silicon-germanium alloy, with a natural lattice constant between about 5.431 Å to 5.657 Å depending on concentration of germanium in the silicon-germanium alloy, larger than that of substrate 300 a. Molar fraction of germanium in the silicon-germanium alloy of lattice-mismatched zone 305 a in accordance with the first embodiment of the present invention is preferably between about 0.1 and 0.9. Therefore, lattice-mismatched zone 305 a as a stressor exerts a compressive stress C₁ in a source-to-drain direction and tensile stress T₁ in a vertical direction on the strained channel region 306 a, resulting in strained channel region 306 a under a compressive strain in the source-to-drain direction and tensile strain in the vertical direction. Hole mobility in the strained channel region 306 a is significantly enhanced, enhancing drive current when strained-channel transistor structure 3 a in accordance with the first embodiment of the present invention is a P-channel transistor structure.

[0032] In FIG. 3B, a cross section of a strained-channel transistor structure 3 b in accordance with the first embodiment of the present invention is shown. Substrate 300 b, having a strained channel region 306 b in a surface, comprises a semiconductor material. Gate dielectric layer 312 b, preferably with a thickness between about 3 and 100 Å, is on the strained channel region 306 b. Gate electrode 314 b is on the gate dielectric layer 312 b. Spacer 316 b is on a sidewall of gate electrode 314 b and covers a part of the surface of substrate 300 b. Drain region 307 b, comprising drain extension region 301 b and deeper drain region 302 b, and source region 308 b, comprising source extension region 303 b and deeper source region 304 b, are oppositely adjacent to strained channel region 306 b. Lattice-mismatched zone 305 b, comprising another semiconductor material with a natural lattice constant different from that of substrate 300 b, may be in one or both of the deeper drain region 302 b and deeper source region 304 b. Strained channel region 306 b is therefore strained by the difference lattice constants of strained channel region 306 b and lattice-mismatched zone 305 b.

[0033] In strained-channel transistor structure 3 b in accordance with the first embodiment of the present invention, substrate 300 b preferably comprises silicon and lattice-mismatched zone 305 b preferably comprises an alloy semiconductor material such as a silicon-carbon alloy, with a natural lattice constant smaller than that of substrate 300 a. Molar fraction of carbon in the silicon-carbon alloy of lattice-mismatched zone 305 b in accordance with the first embodiment of the present invention is preferably between about 0.01 and 0.04. Therefore, lattice-mismatched zone 305 b as a stressor exerts a tensile stress T₂ in a source-to-drain direction and compressive stress C₂ in a vertical direction on the strained channel region 306 b, resulting in strained channel region 306 b under a tensile strain in the source-to-drain direction and compressive strain in the vertical direction. Electron mobility in the strained channel region 306 b is significantly enhanced, enhancing drive current when strained-channel transistor structure 3 b in accordance with the first embodiment of the present invention is an N-channel transistor structure. Furthermore, lattice-mismatched zone 305 b may further comprise germanium as a silicon-germanium-carbon alloy, in which molar fraction of carbon is more than a tenth of that of germanium.

[0034] Further, compressive strain and tensile strain of strained channel region 306 a in FIG. 3A and strained channel region 306 b in FIG. 3B are about 0.1% to 4%, preferably about 1% to 4%. Both lattice-mismatched zone 305 a in FIG. 3A and lattice-mismatched zone 305 b in FIG. 3B are about 10 Å and 1000 Å thick. Compressive strain and tensile strain of strained channel region 306 a in FIG. 3A and strained channel region 306 b in FIG. 3B are dependent on lattice constants of lattice-mismatched zones 306 a and 306 b, thicknesses of lattice-mismatched zones 306 a and 306 b, and arrangement of lattice-mismatched zone 306 a in drain region 307 a and/or source region 308 a, and lattice-mismatched zone 306 b in drain region 307 b and/or source region 308 b.

SECOND EMBODIMENT

[0035] In the second embodiment of the present invention, different kinds of arrangements of lattice-mismatched zone in drain region and/or source region according to the present invention are discussed. In strained-channel transistor structures 4 a through 4d in FIGS. 4A through 4D, relationships among substrate 400, drain extension region 401, deeper drain region 402, drain region 407, source extension region 403, deeper source region 404, source region 408, lattice-mismatched zone 405 a/405 b/ 405 c/ 405 d, strained channel region 406 a/406 b/406 c/ 406 d, gate dielectric layer 412, gate electrode 414, and spacer 416, the same as those described in the first embodiment of the present invention, are omitted.

[0036] In FIG. 4A, lattice-mismatched zone 405 a is arranged near the surface of drain region 407 and/or source region 408, and does not extend into drain extension region 401 and/or source extension region 403. In FIG. 4B, lattice-mismatched zone 405 b may protrude from the surface of drain region 407 and/or source region 408, forming a raised drain region 407 b and raised source region 408 b. In FIG. 4C, lattice-mismatched zone 405 c is arranged near the surface of drain region 407 and/or source region 408, and may further extend into drain extension region 401 and/or source extension region 403. In FIG. 4D, lattice-mismatched zone 405 d is arranged more deeply from the surface of drain region 407 and/or source region 408, and may further extend into strained channel region 406 d beneath drain extension region 401 and/or source extension region 403. Note that the arrangements of lattice-mismatched zone in drain region and/or source region in accordance with the first embodiment of the present invention are not meant to be restrictive. Those skilled in the art may further adjust the arrangement of lattice-mismatched zone according to the present invention when required.

[0037] In FIGS. 4A through 4D, a conductive layer 420 such as silicon, metal, metal silicide, or combinations thereof is optionally formed on the surface of drain region 407 and/or source region 408 of strained-channel transistor structures 4 a, 4 c, and 4 d, and raised drain region 407 b and/or raised source region 408 b of strained-channel transistor structure 4 b.

[0038] Moreover, enhancement of either electron or hole mobility in strained-channel structure 4 c in FIG. 4C is further improved because lattice-mismatched zone 405 c is closer to strained channel region 406 c, resulting in lattice-mismatched zone 405 c exerting more strain on strained channel region 406 c.

THIRD EMBODIMENT

[0039] In the third embodiment of the present invention, a fabrication method of a strained-channel transistor structure according to the present invention is described. A flowchart of the fabrication method in accordance with the third embodiment of the present invention is shown in FIG. 5. The subsequent descriptions of the fabrication method in accordance with the third embodiment of the present invention follow the steps in FIG. 5.

[0040] In FIG. 6A, a semiconductor substrate such as a silicon substrate 500 is provided. Silicon substrate 500 comprises a previously formed plurality of isolation regions (not shown) and previously defined plurality of device regions (not shown). For example, the isolation regions may be shallow trench isolation regions. FIGS. 6A through 6F provide a cross-sectional view of one single device region for easy description. Silicon substrate 500 comprises, a channel region 506 in an active surface. Silicon substrate 500 is N-type doped when strained-channel transistor structure 5 in FIG. 6E is a P-channel transistor structure, or P-type doped when strained-channel transistor structure 5 in FIG. 6E is an N-channel transistor structure.

[0041] In FIG. 6B, a gate dielectric layer 512 is formed on the channel region 506, and then a gate electrode 514 is formed on the gate dielectric layer 512. Gate dielectric layer 512 is formed by thermal oxidation, thermal oxidation followed by nitridation, chemical vapor deposition, physical vapor deposition such as sputtering, or other known techniques to form a gate dielectric layer. Gate dielectric layer 512 can be silicon dioxide, silicon oxynitride, or combinations thereof with a thickness between about 3 A to 100 A, preferably approximately 10 Å or less. Gate dielectric layer 512 may be a high permittivity (high-k) material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiO₄), zirconium silicate (ZrSiO₄), lanthanum oxide (La₂O₃), or combinations thereof with an equivalent oxide thickness between about 3 Å to 100 Å. Gate electrode 514 is polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), refractory metal such as molybdenum or tungsten, compounds such as titanium nitride, combinations thereof or other conductive material(s). Implants known as workfunction implants may be introduced in gate electrode 514 to alter the workfunction thereof. Gate electrode 514 is formed by depositing a gate electrode material layer (not shown) over substrate 500, depositing a gate mask (not shown) over the gate electrode material layer, patterning the gate mask to define gate electrode 514, etching the gate electrode material layer to form gate electrode 514, and removing the gate mask. Gate electrode 514 is electrically isolated from channel region 506 by gate dielectric layer 512. Gate dielectric layer 512 is preferably silicon oxynitride and gate electrode 514 is preferably poly-silicon etched using chlorine and bromine chemistry with a high etch selectivity with respect to gate dielectric later 514 in accordance with the third embodiment of the present invention.

[0042] In FIG. 6C, a drain extension region 501 and source extension region 503 are formed oppositely adjacent to channel region 506 in the active surface of substrate 500, and spacer 516 is formed on a sidewall of gate electrode 514, covering a part of drain extension region 501 and source extension region 503. The drain extension region 501 and source extension region 503 are formed by ion implantation, plasma immersion ion implantation (PIII), or other known techniques. Spacer 516 is preferably formed by depositing a spacer material layer (not shown) such as silicon nitride or silicon dioxide, and selectively etching the spacer material layer. Spacer 516 is silicon nitride in accordance with the third embodiment of the present invention.

[0043] In FIG. 6D, a part or all of the active surface of substrate 500 not covered by gate dielectric layer 512 and spacer 516 is recessed to form at least one recess 509 with a depth d by plasma etching using chlorine and bromine chemistry. The depth d of recess 509 is about 50 Å to 1000 Å. An optional anneal may be performed to facilitate silicon migration to repair etch damage caused by etching recess 509 to smooth the surface of recess 509 for a subsequent epitaxy process.

[0044] In FIG. 6E, recess 509 is filled with a semiconductor material such as silicon-germanium alloy or silicon-carbon alloy to form a lattice-mismatched zone 505, and then a deeper drain region 502 is formed adjacent to the drain extension region 501 and a deeper source region 503 is formed adjacent to the source extension region 502. Deeper drain region 502 combines with drain extension region 501 to form a drain region 507, and deeper source region 504 combines with source extension region 503 to form a source region 508. One or both of the drain region 507 and source region 508 comprise the lattice-mismatched zone 505. Channel region 506 is strained to be a strained channel region 506′ when lattice-mismatched zone 505 is formed. Thus, strained-channel transistor structure 5 in accordance with the third embodiment of the present invention is basically formed. Lattice-mismatched zone 505 is formed using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Lattice-mismatched zone 505 comprises silicon-germanium alloy where molar fraction of germanium is about 0.1 to 0.9 when strained-channel transistor structure 5 is a P-channel transistor structure. When strained-channel transistor structure 5 is an N-channel transistor structure, lattice-mismatched zone 505 comprises silicon-carbon alloy where molar fraction of carbon is between about 0.01 and 0.04, and may further comprise germanium to be silicon-carbon-germanium alloy where molar fraction of germanium is less than ten times that of carbon. A silicon cap 522 is optionally formed on lattice-mismatched zone 505 using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Lattice-mismatched zone 505 and optional silicon cap 522 may be in-situ doped or undoped during the epitaxy process. When lattice-mismatched zone 505 and optional silicon cap 522 are undoped during the epitaxy process, they will be subsequently doped, with dopants activated using a rapid thermal annealing process. Deeper drain region 502 and deeper source region 504 are formed using ion implantation, PIII, gas or solid source diffusion, or other known techniques. An annealing step is further added to recover implant damage or amorphization during formation of lattice-mismatched zone 505, silicon cap 522, deeper drain region 502, and deeper source region 504.

[0045] In FIG. 6F, a conductive layer 520 is optionally formed on lattice-mismatched zone 505 and/or drain region 507/source region 508 to reduce resistances of drain region 507 and source region 508. Conductive layer 520 is formed using self-aligned silicide, or other metal deposition process. Passivation layers and device contacts are subsequently formed so as to finish a device comprising strained-channel transistor structure 5 in accordance with the third embodiment of the present invention.

FOURTH EMBODIMENT

[0046] In the fourth embodiment of the present invention, a fabrication method of a strained-channel transistor structure where lattice-mismatched zone does not extend into drain extension region and/or source extension region according to the present invention is described. A flowchart of the fabrication method in accordance with the third embodiment of the present invention is shown in FIG. 7. The subsequent descriptions of the fabrication method in accordance with the third embodiment of the present invention follow the steps in FIG. 7.

[0047] In FIG. 8A, a semiconductor substrate such as a silicon substrate 600 is provided. Silicon substrate 600 comprises a previously formed plurality of isolation regions (not shown) and previously defined plurality of device regions (not shown). For example, the isolation regions may be shallow trench isolation regions. FIGS. 8A through 8D provide a cross-sectional view of one single device region for easy description. Silicon substrate 600 comprises a conventional transistor structure comprising a channel region 606 in an active surface of substrate 600, a gate dielectric layer 612 on channel region 606, a gate electrode 614 on gate dielectric layer 612, a source region 608 and drain region 607 oppositely adjacent to channel region 606, and a spacer 616 on a sidewall of gate electrode 614, covering a part of the active surface of substrate 600. Drain region 607 comprises a drain extension region 601 and a deeper drain region 602, and source region 608 comprises a source extension region 603 and a deeper source region 604. Silicon substrate 600 is N-type doped when strained-channel transistor structure 6 in FIG. 8C is a P-channel transistor structure, or P-type doped when strained-channel transistor structure 6 in FIG. 8C is an N-channel transistor structure.

[0048] In FIG. 8B, a part or all of the active surface of substrate 600 not covered by gate dielectric layer 612 and spacer 616 is recessed to form at least one recess 609 with a depth d by plasma etching using chlorine and bromine chemistry. The depth d of recess 609 is about 50 Å to 1000 Å. An optional anneal may be performed to facilitate silicon migration to repair etch damage caused by etching recess 606 to smooth the surface of recess 609 for a subsequent epitaxy process.

[0049] In FIG. 8C, recess 609 is filled with a semiconductor material such as silicon-germanium alloy or silicon-carbon alloy to form a lattice-mismatched zone 605. One or both of the drain region 607 and source region 608 comprise the lattice-mismatched zone 605. Channel region 606 is strained to be a strained channel region 606′ when lattice-mismatched zone 605 is formed. Thus, strained-channel transistor structure 6 in accordance with the fourth embodiment of the present invention is basically formed. Lattice-mismatched zone 605 may protrude from the surface of drain region 607 and/or source region 608, forming a raised drain region and raised source region. Lattice-mismatched zone 605 is formed using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Lattice-mismatched zone 605 comprises silicon-germanium alloy where molar fraction of germanium is about 0.1 to 0.9 when strained-channel transistor structure 6 is a P-channel transistor structure. When strained-channel transistor structure 6 is an N-channel transistor structure, lattice-mismatched zone 605 comprises silicon-carbon alloy where molar fraction of carbon is between about 0.01 and 0.04, and may further comprise germanium to be silicon-carbon-germanium alloy where molar fraction of germanium is less than ten times that of carbon. A silicon cap 622 is optionally formed on lattice-mismatched zone 605 using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Lattice-mismatched zone 605 and optional silicon cap 622 are in-situ doped during the epitaxy process.

[0050] In FIG. 8D, a conductive layer 620 is optionally formed on lattice-mismatched zone 605 and/or drain region 607/source region 608 to reduce resistances of drain region 607 and source region 608. Conductive layer 620 is formed using self-aligned silicide, or other metal deposition process. Passivation layers and device contacts are subsequently formed so as to finish a device comprising strained-channel transistor structure 6 in accordance with the third embodiment of the present invention.

FIFTH EMBODIMENT

[0051] In the fifth embodiment of the present invention, a fabrication method of a strained-channel transistor structure where lattice-mismatched zone extends into drain extension region and/or source extension region according to the present invention is described. A flowchart of the fabrication method in accordance with the third embodiment of the present invention is shown in FIG. 9. The subsequent descriptions of the fabrication method in accordance with the third embodiment of the present invention follow the steps in FIG. 9.

[0052] In FIG. 10A, a semiconductor substrate such as a silicon substrate 700 is provided. Silicon substrate 700 comprises a previously formed plurality of isolation regions (not shown) and previously defined plurality of device regions (not shown). For example, the isolation regions may be shallow trench isolation regions. FIGS. 10A through 10G provide a cross-sectional view of one single device region for easy description. Silicon substrate 700 comprises a channel region 706 in an active surface. Silicon substrate 700 is N-type doped when strained-channel transistor structure 7 in FIG. 10D is a P-channel transistor structure, or P-type doped when strained-channel transistor structure 7 in FIG. 10D is an N-channel transistor structure.

[0053] In FIG. 10B, first, a gate dielectric layer 712 is formed on the channel region 706, and a gate electrode 714 is formed on the gate dielectric layer 712. Finally, spacer 715 is formed on a sidewall of gate electrode 714, covering a part of the active surface of substrate 700. Gate dielectric layer 712 is formed by thermal oxidation, thermal oxidation followed by nitridation, chemical vapor deposition, physical vapor deposition such as sputtering, or other known techniques to form a gate dielectric layer. Gate dielectric layer 712 is preferably silicon dioxide, silicon oxynitride, or combinations thereof with a thickness between about 3 Å to 100 Å, preferably approximately 10 Å or less. Gate dielectric layer 712 may be a high permittivity (high-k) material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiO₄), zirconium silicate (ZrSiO₄), lanthanum oxide (La₂O₃), or combinations thereof with an equivalent oxide thickness between about 3 Å to 100 Å. Gate electrode 714 is polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), refractory metal such as molybdenum or tungsten, compounds such as titanium nitride, combinations thereof or other conductive material(s). Implants known as workfunction implants may be introduced in gate electrode 714 to alter the workfunction thereof. Gate electrode 714 is formed by depositing a gate electrode material layer (not shown) over substrate 700, depositing a gate mask (not shown) over the gate electrode material layer, patterning the gate mask to define gate electrode 714, etching the gate electrode material layer to form gate electrode 714, and removing the gate mask. Gate electrode 714 is electrically isolated from channel region 706 by gate dielectric layer 712. Gate dielectric layer 712 is preferably silicon oxynitride and gate electrode 714 is poly-silicon etched using chlorine and bromine chemistry with a high etch selectivity with respect to gate dielectric later 714 in accordance with the third embodiment of the present invention. Spacer 715 is formed using a deposition and anisotropic etching technique for protecting the sidewall of gate electrode 714 during a subsequent epitaxy step.

[0054] In FIG. 10C, a part or all of the active surface of substrate 700 not covered by gate dielectric layer 712 and spacer 715 is recessed to form at least one recess 709 with a depth d by plasma etching using chlorine and bromine chemistry. The depth d of recess 709 is about 50 Å to 1000 Å. An optional anneal may be performed to facilitate silicon migration to repair etch damage caused by etching recess 706 to smooth the surface of recess 709 for a subsequent epitaxy process.

[0055] In FIG. 10D, recess 709 is filled with a semiconductor material such as silicon-germanium alloy or silicon-carbon alloy to form a lattice-mismatched zone 505, and then a drain extension region 701 and source extension region 702 are formed oppositely adjacent to the strained channel region 706′. Thus, strained-channel transistor structure 7 in accordance with the fifth embodiment of the present invention is basically formed. Lattice-mismatched zone 705 is formed using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Channel region 706 is strained to be a strained channel region 706′ when lattice-mismatched zone 705 is formed. Lattice-mismatched zone 705 comprises silicon-germanium alloy where molar fraction of germanium is about 0.1 to 0.9 when strained-channel transistor structure 7 is a P-channel transistor structure. When strained-channel transistor structure 7 is an N-channel transistor structure, lattice-mismatched zone 705 comprises silicon-carbon alloy where molar fraction of carbon is between about 0.01 and 0.04, and may further comprise germanium to be silicon-carbon-germanium alloy where molar fraction of germanium is less than ten times that of carbon. A silicon cap 722 is optionally formed on-lattice-mismatched zone 705 using an epitaxy process such as chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. Lattice-mismatched zone 705 and optional silicon cap 722 may be in-situ doped or undoped during the epitaxy process. When lattice-mismatched zone 705 and optional silicon cap 722 are undoped during the epitaxy process, but will be doped subsequently, at which time dopants will be activated using a rapid thermal annealing process. Drain extension region 701 and source extension region 703 are formed by dopant diffusion from lattice-mismatched zone 705 and optional silicon cap 722. One or both of the drain extension region 701 and source extension region 703 comprise the lattice-mismatched zone 705 and optional silicon cap 722.

[0056] In FIG. 10E, a spacer 716 is formed overlying the spacer 715. Spacer 716 is formed using deposition and selectively etching a spacer material (not shown) such as silicon nitride or silicon dioxide. Spacer 716 is silicon nitride in accordance with the third embodiment of the present invention.

[0057] In FIG. 10F, a deeper drain region 702 is formed adjacent to drain extension region 701, and deeper source region 704 is formed adjacent to source extension region 702. Deeper drain region 702 combines with drain extension region 701, lattice-mismatched zone 705 when available, and optional silicon cap 722 when available to be a drain region 707, and deeper source region 704 combines with source extension region 703, lattice-mismatched zone 705 when available, and optional silicon cap 722 when available to be a source region 708. Deeper drain region 702 and deeper source region 704 are formed using ion implantation, PIII, gas or solid source diffusion, or other known techniques.

[0058] In FIG. 10G, a conductive layer 720 is optionally formed on drain region 707 and source region 708 to reduce resistances of drain region 707 and source region 708. Conductive layer 720 is formed using self-aligned silicide, or other metal deposition. Passivation layers and device contacts are subsequently formed so as to finish a device comprising strained-channel transistor structure 7 in accordance with the fifth embodiment of the present invention.

SIXTH EMBODIMENT

[0059] In the sixth embodiment of the present invention, a fabrication method of a strained-channel transistor structure where lattice-mismatched zone is formed using an ion implantation process according to the present invention is described.

[0060] In FIG. 11A, a semiconductor substrate such as a silicon substrate 800 is provided. Silicon substrate 800 comprises a previously formed plurality of isolation regions (not shown) and previously defined plurality of device regions (not shown). For example, the isolation regions may be shallow trench isolation regions. FIGS. 11A through 11D provide a cross-sectional view of one single device region for easy description. Silicon substrate 800 comprises a conventional transistor structure comprising a channel region 806 in an active surface of substrate 800, a gate dielectric layer 812 on channel region 806, a gate electrode 814 on gate dielectric layer 812, a source region 808 and drain region 807 oppositely adjacent to channel region 806, and a spacer 816 on a sidewall of gate electrode 814, covering a part of the active surface of substrate 800. Drain region 807 comprises a drain extension region 801 and a deeper drain region 802, and source region 808 comprises a source extension region 803 and a deeper source region 804. Silicon substrate 800 is N-type doped when strained-channel transistor structure 8 in FIG. 11C is a P-channel transistor structure, or P-type doped when strained-channel transistor structure 8 in FIG. 11C is an N-channel transistor structure.

[0061] In FIG. 11B, an ion implantation process is performed to introduce ions 830 of one or more atomic species with a different atomic size from that of substrate 800 into drain region 807 and/or source region 808. Gate electrode 814 and spacer 816 act as a implantation mask during the ion implantation process. Thickness of spacer 816 is adjustable depending on lattice-mismatched zone 805 in FIG. 11C either extending into drain extension region 801 and/or source extension region 803, or not extending into drain extension region 801 and/or source extension region 803, as required.

[0062] In FIG. 1C, an annealing step is performed on the substrate 800 to form a lattice-mismatched zone in one or both of drain region 807 and source region 808. Thus, one or both of the drain region 807 and source region 808 comprise the lattice-mismatched zone 805. Channel region 806 is strained to be a strained channel region 806′ when lattice-mismatched zone 805 is formed. Thus, strained-channel transistor structure 8 in accordance with the sixth embodiment of the present invention is basically formed. Lattice-mismatched zone 805 comprises silicon-germanium alloy where molar fraction of germanium is about 0.1 to 0.9 when strained-channel transistor structure 8 is a P-channel transistor structure. When strained-channel transistor structure 8 is an N-channel transistor structure, lattice-mismatched zone 805 comprises silicon-carbon alloy where molar fraction of carbon is between about 0.01 and 0.04, and may further comprise germanium to be silicon-carbon-germanium alloy where molar fraction of germanium is less than ten times that of carbon.

[0063] In FIG. 11D, a conductive layer 820 is optionally formed on drain region 807 and source region 808 to reduce resistances of drain region 807 and source region 808. Conductive layer 820 is formed using self-aligned silicide, or other metal deposition process. Passivation layers and device contacts are subsequently formed so as to finish a device comprising strained-channel transistor structure 8 in accordance with the sixth embodiment of the present invention.

[0064] Although the present invention has been particularly shown and described above with reference to six specific embodiments, it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alteration and modifications as fall within the true spirit and scope of the present invention. 

What is claimed is:
 1. A strained-channel transistor structure with improved transport properties, comprising: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.
 2. The transistor structure as claimed in claim 1, wherein the lattice-mismatched zone is about 10 to 1000 Å thick.
 3. The transistor structure as claimed in claim 1, wherein the lattice-mismatched zone is about 300 to 1000 Å thick.
 4. The transistor structure as claimed in claim 1, wherein the first semiconductor material comprises silicon.
 5. The transistor structure as claimed in claim 1, wherein the second semiconductor comprises silicon and germanium.
 6. The transistor structure as claimed in claim 1, wherein the second semiconductor comprises silicon and carbon.
 7. The transistor structure as claimed in claim 5, wherein molar fraction of germanium in the second semiconductor material is about 0.1 to 0.9.
 8. The transistor structure as claimed in claim 6, wherein molar fraction of carbon in the second semiconductor material is about 0.01 to 0.04.
 9. The transistor structure as claimed in claim 6, wherein the second semiconductor material further comprises germanium whose molar fraction in the second semiconductor material is less than ten times that of carbon in the second semiconductor material.
 10. The transistor structure as claimed in claim 1, wherein the strained channel region is under a tensile strain in a source-to-drain direction.
 11. The transistor structure as claimed in claim 1, wherein the strained channel region is under a compressive strain in a vertical direction.
 12. The transistor structure as claimed in claim 10, wherein the tensile strain is about 0.1% to 4%.
 13. The transistor structure as claimed in claim 11, wherein the compressive strain is about 0.1% to 4%.
 14. The transistor structure as claimed in claim 1, wherein the strained channel region is under a compressive strain in a source-to-drain direction.
 15. The transistor structure as claimed in claim 1, wherein the strained channel region is under a tensile strain in a vertical direction.
 16. The transistor structure as claimed in claim 14, wherein the compressive strain is about 0.1% to 4%.
 17. The transistor structure as claimed in claim 15, wherein the tensile strain is about 0.1% to 4%.
 18. The transistor structure as claimed in claim 1, further comprising a cap layer on the lattice-mismatched zone.
 19. The transistor structure as claimed in claim 18, wherein the cap layer comprises the first semiconductor material.
 20. The transistor structure as claimed in claim 1, wherein the source region comprises a source extension region and a deep source region, and the drain region comprises a drain extension region and a deep drain region.
 21. The transistor structure as claimed in claim 20, wherein the lattice-mismatched zone laterally extends into the source extension region and/or drain extension region.
 22. The transistor structure as claimed in claim 1, wherein the lattice-mismatched zone further extends beyond the source region and/or drain region.
 23. The transistor structure as claimed in claim 1, wherein the gate dielectric layer is silicon oxide or silicon oxynitride.
 24. The transistor structure as claimed in claim 1, wherein the gate dielectric layer is Al₂O₃, HfO₂, ZrO₂, HfON, HfSiO₄, ZrSiO₄, La₂O₃, or combinations thereof.
 25. The transistor structure as claimed in claim 24, wherein the relative permittivity of the gate dielectric layer is larger than
 5. 26. The transistor structure as claimed in claim 1, wherein the gate dielectric layer is about 3 to 100 Å thick.
 27. The transistor structure as claimed in claim 1, wherein the gate electrode comprises poly-crystalline silicon.
 28. The transistor structure as claimed in claim 1, wherein the gate electrode comprises poly-crystalline silicon germanium.
 29. The transistor structure as claimed in claim 1, wherein the gate electrode comprises a metal.
 30. The transistor structure as claimed in claim 1, wherein the gate electrode comprises a metal silicide.
 31. The transistor structure as claimed in claim 1, further comprising a conductive material on the source region and drain region.
 32. The transistor structure as claimed in claim 31, wherein the conductive material comprises a metal.
 33. The transistor structure as claimed in claim 31, wherein the conductive material comprises a metal silicide.
 34. A method of fabrication a strained-channel transistor structure with improved transport properties, comprising: providing a substrate comprising a first semiconductor material with a first natural lattice constant, a gate dielectric layer on the substrate, and a gate electrode on the gate dielectric layer; forming a first source region and first drain region oppositely adjacent to the gate dielectric layer; forming a spacer on a sidewall of the gate electrode; recessing the surface of the substrate not covered by the spacer and gate dielectric layer to form a recess; filling the recess with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone; and forming a second source region adjacent to the first source region and second drain region adjacent to the first drain region, one or both of the second source region and second drain region comprising the lattice-mismatched zone.
 35. The method as claimed in claim 34, wherein the first semiconductor material comprises silicon.
 36. The method as claimed in claim 34, wherein the second semiconductor comprises silicon and germanium.
 37. The method as claimed in claim 34, wherein the second semiconductor comprises silicon and carbon.
 38. The method as claimed in claim 36, wherein molar fraction of germanium in the second semiconductor material is about 0.1 to 0.9.
 39. The method as claimed in claim 37, wherein molar fraction of carbon in the second semiconductor material is about 0.01 to 0.04.
 40. The method as claimed in claim 37, wherein the second semiconductor material further comprises germanium whose molar fraction in the second semiconductor material is less than ten times that of carbon in the second semiconductor material.
 41. The method as claimed in claim 34, wherein the recess is formed by plasma etching.
 42. The method as claimed in claim 34, wherein the recess is about 50 to 1000 Å deep.
 43. The method as claimed in claim 34, further comprising annealing the substrate in an inert ambient after forming the recess.
 44. The method as claimed in claim 34, wherein the second semiconductor material is filled in the recess by an epitaxy process using chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy.
 45. The method as claimed in claim 34, wherein the second semiconductor material is in-situ doped when filling the recess.
 46. The method as claimed in claim 34, wherein the second semiconductor material is undoped when filling the recess.
 47. The method as claimed in claim 34, further comprising forming a cap layer on the second semiconductor material.
 48. The method as claimed in claim 47, wherein the cap layer comprises the first semiconductor material.
 49. The method as claimed in claim 34, wherein the gate dielectric layer comprises silicon oxide or silicon oxynitride.
 50. The method as claimed in claim 34, wherein the gate dielectric layer is Al₂O₃, HfO₂, ZrO₂, HfON, HfSiO₄, ZrSiO₄, La₂O₃, or combinations thereof.
 51. The method as claimed in claim 50, wherein the relative permittivity of the gate dielectric layer is larger than
 5. 52. The method as claimed in claim 34, wherein the gate dielectric layer is about 3 to 100 Å thick.
 53. The method as claimed in claim 34, wherein the gate electrode comprises poly-crystalline silicon.
 54. The method as claimed in claim 34, wherein the gate electrode comprises poly-crystalline silicon germanium.
 55. The method as claimed in claim 34, wherein the gate electrode comprises a metal.
 56. The method as claimed in claim 34, wherein the gate electrode comprises a metal silicide.
 57. The method as claimed in claim 34, wherein the first source region and first drain region are formed by ion implantation or plasma immersion ion implantation.
 58. The method as claimed in claim 34, wherein the second source region and second drain region are formed by ion implantation or plasma immersion ion implantation.
 59. The method as claimed in claim 34, further comprising forming a conductive material on the second source region and second drain region.
 60. The method as claimed in claim 59, wherein the conductive material comprises a metal.
 61. The method as claimed in claim 59, wherein the conductive material comprises a metal silicide.
 62. A method of fabrication a strained-channel transistor structure with improved transport properties, comprising: providing a substrate comprising a first semiconductor material with a first natural lattice constant, a gate dielectric layer on the substrate, a gate electrode on the gate dielectric layer, a source region and drain region oppositely adjacent to the gate dielectric layer, and a spacer on a sidewall of the gate electrode; recessing one or both of the source region and drain region to form a recess; and filling the recess with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone.
 63. The method as claimed in claim 62, wherein the first semiconductor material comprises silicon.
 64. The method as claimed in claim 62, wherein the second semiconductor comprises silicon and germanium.
 65. The method as claimed in claim 62, wherein the second semiconductor comprises silicon and carbon.
 66. The method as claimed in claim 64, wherein molar fraction of germanium in the second semiconductor material is about 0.1 to 0.9.
 67. The method as claimed in claim 65, wherein molar fraction of carbon in the second semiconductor material is about 0.01 to 0.04.
 68. The method as claimed in claim 65, wherein the second semiconductor material further comprises germanium whose molar fraction in the second semiconductor material is less than ten times that of carbon in the second semiconductor material.
 69. The method as claimed in claim 62, wherein the recess is formed by plasma etching.
 70. The method as claimed in claim 62, wherein the recess is about 50 to 1000 Å deep.
 71. The method as claimed in claim 62, further comprising annealing the substrate in an inert ambient after forming the recess.
 72. The method as claimed in claim 62, wherein the second semiconductor material is filled in the recess by an epitaxy process using chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy.
 73. The method as claimed in claim 62, wherein the second semiconductor material is in-situ doped when filling the recess.
 74. The method as claimed in claim 62, further comprising forming a cap layer on the second semiconductor material.
 75. The method as claimed in claim 74, wherein the cap layer comprises the first semiconductor material.
 76. The method as claimed in claim 62, wherein the gate dielectric layer comprises silicon oxide or silicon oxynitride.
 77. The method as claimed in claim 62, wherein the gate dielectric layer comprises Al₂O₃, HfO₂, ZrO₂, HfON, HfSiO₄, ZrSiO₄, La₂O₃, or combinations thereof.
 78. The method as claimed in claim 77, wherein the relative permittivity of the gate dielectric layer is larger than
 5. 79. The method as claimed in claim 62, wherein the gate dielectric layer is about 3 to 100 Å thick.
 80. The method as claimed in claim 62, wherein the gate electrode comprises poly-crystalline silicon.
 81. The method as claimed in claim 62, wherein the gate electrode comprises poly-crystalline silicon germanium.
 82. The method as claimed in claim 62, wherein the gate electrode comprises a metal.
 83. The method as claimed in claim 62, wherein the gate electrode comprises a metal silicide.
 84. The method as claimed in claim 62, further comprising forming a conductive material on the source region and drain region.
 85. The method as claimed in claim 84, wherein the conductive material comprises a metal.
 86. The method as claimed in claim 84, wherein the conductive material comprises a metal silicide.
 87. A method of fabrication a strained-channel transistor structure with improved transport properties, comprising: providing a substrate comprising a first semiconductor material with a first natural lattice constant, a gate dielectric layer on the substrate, a gate electrode on the gate dielectric layer, and a first spacer on a sidewall of the gate electrode; recessing the surface of the substrate not covered by the spacer and gate dielectric layer to form a recess; filling the recess with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone; and forming a first source region and second drain region oppositely adjacent to the gate dielectric layer, one or both of the first source region and second drain region comprising the lattice-mismatched zone.
 88. The method as claimed in claim 87, further comprising: forming a second spacer overlying the first spacer; and forming a second source region adjacent to the first source region and second drain region adjacent to the first drain region.
 89. The method as claimed in claim 87, wherein the second semiconductor material is in-situ doped when filling the recess.
 90. The method as claimed in claim 87, wherein the second semiconductor material is undoped when filling the recess.
 91. The method as claimed in claim 87, wherein the first source region and first drain region are formed by ion implantation or plasma immersion ion implantation.
 92. The method as claimed in claim 87, wherein the first semiconductor material comprises silicon.
 93. The method as claimed in claim 87, wherein the second semiconductor comprises silicon and germanium.
 94. The method as claimed in claim 87, wherein the second semiconductor comprises silicon and carbon.
 95. The method as claimed in claim 93, wherein molar fraction of germanium in the second semiconductor material is about 0.1 to 0.9.
 96. The method as claimed in claim 94, wherein molar fraction of carbon in the second semiconductor material is about 0.01 to 0.04.
 97. The method as claimed in claim 94, wherein the second semiconductor material further comprises germanium whose molar fraction in the second semiconductor material is less than ten times that of carbon in the second semiconductor material.
 98. The method as claimed in claim 87, wherein the recess is formed by plasma etching.
 99. The method as claimed in claim 87, wherein the recess is about 50 to 1000 Å deep.
 100. The method as claimed in claim 87, further comprising annealing the substrate in an inert ambient after forming the recess.
 101. The method as claimed in claim 87, wherein the second semiconductor material is filled in the recess by an epitaxy process using chemical vapor deposition, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy.
 102. The method as claimed in claim 87, further comprising forming a cap layer on the second semiconductor material.
 103. The method as claimed in claim 102, wherein the cap layer comprises the first semiconductor material.
 104. The method as claimed in claim 87, wherein the gate dielectric layer comprises silicon oxide or silicon oxynitride.
 105. The method as claimed in claim 87, wherein the gate dielectric layer comprises Al₂O₃, HfO₂, ZrO₂, HfON, HfSiO₄, ZrSiO₄, La₂O₃, or combinations thereof.
 106. The method as claimed in claim 87, wherein the relative permittivity of the gate dielectric layer is larger than
 5. 107. The method as claimed in claim 87, wherein the gate dielectric layer is about 3 to 100 Å thick.
 108. The method as claimed in claim 87, wherein the gate electrode comprises poly-crystalline silicon.
 109. The method as claimed in claim 87, wherein the gate electrode comprises poly-crystalline silicon germanium.
 110. The method as claimed in claim 87, wherein the gate electrode comprises a metal.
 111. The method as claimed in claim 87, wherein the gate electrode comprises a metal silicide.
 112. The method as claimed in claim 88, wherein the second source region and second drain region are formed by ion implantation or plasma immersion ion implantation.
 113. The method as claimed in claim 87, further comprising forming a conductive material on the first source region and first drain region.
 114. The method as claimed in claim 113, wherein the conductive material comprises a metal.
 115. The method as claimed in claim 113, wherein the conductive material comprises a metal silicide.
 116. A method of fabrication a strained-channel transistor structure with improved transport properties, comprising: providing a substrate comprising a semiconductor material, a gate dielectric layer on the substrate, a gate electrode on the gate dielectric layer, and a source region and drain region oppositely adjacent to the gate dielectric layer; and implanting an element with an atomic size different from that of the semiconductor material to form a lattice-mismatched zone in one or both of the source region and drain region.
 117. The method as claimed in claim 116, further comprising annealing the substrate after implanting the element.
 118. The method as claimed in claim 116, wherein the first semiconductor comprises silicon.
 119. The method as claimed in claim 116, wherein the element is germanium.
 120. The method as claimed in claim 116, wherein the element is carbon.
 121. The method as claimed in claim 119, wherein molar fraction of germanium in the lattice-mismatched zone is about 0.1 to 0.9.
 122. The method as claimed in claim 120, wherein molar fraction of carbon in the lattice-mismatched zone is about 0.01 to 0.04.
 123. The method as claimed in claim 116, wherein the gate dielectric layer comprises silicon oxide or silicon oxynitride.
 124. The method as claimed in claim 124, wherein the gate dielectric layer comprises Al₂O₃, HfO₂, ZrO₂, HfON, HfSiO₄, ZrSiO₄, La₂O₃, or combinations thereof.
 125. The method as claimed in claim 124, wherein the relative permittivity of the gate dielectric layer is larger than
 5. 126. The method as claimed in claim 116, wherein the gate dielectric layer is about 3 to 100 Å thick.
 127. The method as claimed in claim 116, wherein the gate electrode comprises poly-crystalline silicon.
 128. The method as claimed in claim 116, wherein the gate electrode comprises poly-crystalline silicon germanium.
 129. The method as claimed in claim 116, wherein the gate electrode comprises a metal.
 130. The method as claimed in claim 116, wherein the gate electrode comprises a metal silicide.
 131. The method as claimed in claim 116, further comprising forming a conductive material on the source region and drain region.
 132. The method as claimed in claim 116, wherein the conductive material comprises a metal.
 133. The method as claimed in claim 116, wherein the conductive material comprises a metal silicide. 